The present invention relates to a process for manufacturing a DMOS transistor.
Such a process is known from the printed publication U.S. Pat. No. 5,539,238. Here, a DMOS transistor with a deep trench structure is generated, with the doped regions adjoining the side walls and the base region representing the so-called drift zone of the transistor. Due to the partially vertical implementation of the drift zone along the side walls of the trench, the length of the transistor can be reduced. The disadvantage in this process is that for an applied blocking voltage inhomogeneities in the course of the potential occur on the edges of the trench structure, which cause an undesirable reduction in the transistor blocking voltage. Furthermore, the total length of the drift region is not decreased but only subdivided into a vertical and a lateral share, that is, the specific turn-on resistance Rsp=Rdson/region is not decreased, rather the side walls can only be doped insufficiently; and the specific turn-on resistance, and thus the surface area used by the transistor, are increased.
A further process is known from the printed publication EP 0 837 509 Al. Here, a self-adjusted drift region is generated in a DMOS transistor below a LOCOS oxide. The disadvantage is that the doping of the drift region is introduced before oxidation and that the share of the doping agent diffusing into the oxide can be determined with some imprecision only. In addition, the high temperature load during oxidation causes a wide distribution of the doping agent, which in turn leads to a higher imprecision in the doping agent concentration. Furthermore, a large silicon thickness is required underneath the oxide in order to increase the blocking voltage by means of the so-called xe2x80x9cRESURFxe2x80x9d effect. Overall, the process scatterings increase the scatter in the electrical parameters of the transistor. One development aim in the area of DMOS transistors is to manufacture space-saving structures which, for an applied blocking voltage, feature low field strengths, in order to avoid a generation of load carriers that lead to a breakthrough within the component. A further aim in the development of DMOS transistors is to achieve a low specific turn-on resistance, Rsp, in order to reduce the spatial area required by such an integrated circuit in the case of integrated circuits where DMOS transistors take up a significant part of the total chip surface area.
The present invention is based on the task to state a process by means of which DMOS transistors can be provided on a compact surface area for high blocking voltages.
The above object has been achieved according to the invention by a process as defined in the claims.
In accordance with the above, the invention essentially provides a process wherein a trench-shaped structure is generated in a DMOS transistor where, by selecting the doping agent profile within the region of the trench-shaped structure, a high breakthrough voltage for a low lateral expansion of the DMOS transistor is achieved. As produced by this process, a semiconductor body of a first conductivity type features a surface layer in which a source region end a drain region of a second conductivity type, and a first well region of a first conductivity type that encloses the source region, and a second well region of a second conductivity type that encloses the drain region, are formed. Also, on the surface of the semiconductor body, a gate region is formed, whichxe2x80x94starting at the source regionxe2x80x94extends fully across the veil region of the first conductivity type. Still further, starting at the surface of the semiconductor body the trench-shaped structure is formed in a part of the surface layer. In the floor region of the trench-shaped structure, a doping of a second conductivity type with a first concentration, and in the source-end side wall of the trench-shaped structure a doping of the second conductivity type with a second concentration, and in the drain-end side wall of the trench-shaped structure a doping of the second conductivity type with a third concentration, are generated.
An essential advantage of the new process is that, due to the different concentration of the doping agent in the source-end side wall compared to the drain-end side wall in connection with the doping agent concentration in the floor region of the trench-shaped structure, which together define the drift range of the transistor, a simple optimization within a parameter field essentially determined by the specific turn-on resistance Rsp, breakthrough voltage Vbreak, and the size and shape of the SOA (safe-operation-area), can be carried out. In particular for driver structures it thus becomes possible to generate transistors with a compact total area. Furthermore, the RESURF effect can be optimized particularly advantageously with regard to: starting point, using different doping agent concentrations; strength, by means of an adjustable vertical distribution of the potential gradient for the applied blocking voltage. As doping is effected only after silicon etching with a low implantation energy, and no thick LOCOS-oxide with a high temperature load is generated next, spatially highly doped regions can be generated along a short vertical route underneath the floor of the trench-shaped structure; these spatially highly doped regions form a buried current path with low resistance. As the doping of the floorxe2x80x94by means of the RESURF-effect in connection with the doping course in the source-end side wallxe2x80x94has an essential influence on the breakthrough voltage in a blocking as well as in a switched on condition, whilst the drain-end doping agent course has an essential influence on the turn-on resistance Rdson, an adaptation of the doping profiles along the trench-shaped structure to the electrical requirements is particularly advantageous. Furthermore, the space used by the transistors is reduced as, due to the self-adjustment in connection with a simultaneously reduced temperature load compared with a LOCOS oxidation, the process scattering of the doping agent profiles introduced into the trench-shaped structure are reduced.
In a further embodiment of the process, it is advantageous to expand the region of the second well in the direction of the source and to generate the trench-shaped structure partially or wholly within the region of the second well. The further the second well extends in the direction of the source, the more the specific turn-on resistance Rsp is reduced, as the floor region of the trench-shaped structure and the second well feature the same doping polarity. At the same time the transistor features a high breakthrough voltage as the concentration of the dopings for the first and second wells is significantly lower than the concentration of the source and drain regions. Furthermore, both wells can be produced by means of LOCOS oxidation in a single mask step and with self-adjustment. It is advantageous here, to drive in the first well more deeply and for a greater length in order to generate a RESURF effect underneath the trench-shaped structure by means of a lateral PN junction, which RESURF effect increases the breakthrough voltage.
In a further embodiment of the process, an extension region is generated underneath the drain-doping region, which extension region completely encloses the drain region, with the doping of the extension region being of the same conductivity type, but featuring a lower concentration than the drain region. In addition to the suppression of a drain-end breakthrough, the reduction of the resistance within the drain-end side wall region reduces the specific turn-on resistance Rsp. The specific turn-on resistance Rsp is reduced particularly strongly if the extension region and/or the drain-end region connect immediately to the drain-end side wall of the trench-shaped structure.
Investigations carried out by the applicant have shown that in the breakthrough region of the transistor, by means of a distance between the drain-end side wall of the trench-shaped structure and the extension region and/or the drain-endxe2x80x94which is preferably between 0.5 xcexcm and 4.0 xcexcmxe2x80x94, a balancing can be achieved. Here, by means of the additional drain-end resistance causing a voltage drop, a local excessive increase in the current density is suppressed. In particular in connection with a clamp controller, advantageous ESD protective structures can be produced by means of such transistors.
In a further development of the process, in the side walls and in the floor region of the trench-shaped structure, a higher doping agent concentration than in the body region is generated, in order to increase the maximum blocking voltage by means of the RESURF effect, and also to reduce the specific turn-on resistance Rsp.
In another development of the process, the same doping agent concentration is generated in the source-end side wall as well as in the drain-end side wall of the trench-shaped structure. This simplifies the introduction of the doping agent and increases the specific turn-on resistance Rsp by only a minor degree, as the individual doping agent concentrations add up, if the extension region and the drain region start immediately on the side wall of the trench-shaped structure, and if the introduction depth of the drain-end doping lies within the range of the trench-shaped structure. Furthermore, it is advantageousxe2x80x94in particular with regard to deep trench-shaped structuresxe2x80x94to generate a higher doping agent concentration in the drain-end side wall than in the source-end side wall, in order to obtain a lower turn-on resistance Rsp.
Investigations by the applicant with regard to different doping agent concentrations for wall and floor have shown that it is advantageous, if the aspect ratio of the trench-shaped structure is above 0.5, and features a trench-shaped structure with a width in a range between 0.5 xcexcm and 4.0 xcexcm. In order to suppress excessive field strength increases on the edges of the trench-shaped structure, it is advantageous to generate inclined side walls, that is, the trench-shaped structure features a narrower width in the floor region than on the surface. The generation of the trench-shaped structure can be carried out by means of a dry etching process such as, for example, a shallow trench process (STI), and filled up with an isolating material such as a CVD-oxide or nitride, and planarized by the use of a CMP process.
In another development of the process, the trench-shaped structure is generated by means of a V trench etching process and filled up in a following LOCOS oxidation which, due to the lower temperature load, is preferably produced by high pressure oxidation. The doping of the side walls and the floor is carried out prior to the LOCOS oxidation, with the infed dosage of doping agents being increased by that proportion which is diffused into the oxide during oxidation.
In a further development of the process, the DMOS transistor is generated in the surface layer of a wafer with an isolating intermediate layer. It is advantageous here, if the thickness of the residual surface layer underneath the trench-shaped structure is between one half and a factor 5 of the depth of the trench-shaped structure. It is furthermore advantageous, if the drain-end region and/or extension region, and the two well regions as well as the source region connect immediately to the isolating intermediate layer in order to suppress the parasitic capacitances. A further advantage is that the required layer thickn ss of the surface layer is within a range of just a few xcexcm, as the formation of a highly doped buried channel connecting to the floor of the trench-shaped structure features only a low vertical extension.
Investigations by the applicant have shown that the DMOS transistors produced by the process in accordance with the invention, in particular when using a silicon wafer with an isolating intermediate layer, are especially suitable for the manufacture of high blocking integrated circuits featuring an output driver for driving inductive loads.